The present invention relates generally to integrated circuit metallization, and more particularly to a methods of forming metallization by planarizing copper wiring wherein a liner is used under a copper layer.
In the field of integrated circuit manufacturing, it is well known that significant density advantages result from forming planar metallization patterns which interconnect one or more transistors, capacitors, resistors, and other semiconductor electronic components formed on a wafer. One of the significant trends in the industry is produce such planar metallization patterns using so-called xe2x80x9cChemical-Mechanical Planarizationxe2x80x9d or xe2x80x9cChem-Mech Polishxe2x80x9d or just xe2x80x9cCMPxe2x80x9d techniques. In CMP, the front side of a semiconductor wafer is held against a rotating polish wheel, and a polishing slurry is introduced that facilitates the planarization and partial removal of a metal layer on the wafer through a combination of chemical reaction and physical abrasion. See for example U.S. Pat. No. 4,944,836, issued Jul. 31, 1990 to Beyer et al. and assigned to the assignee of the present invention, which teaches the CMP of metals or insulators to form coplanar insulator/metal films.
In addition to the general advantages afforded by CMP, particular density advantages result from forming an integrated metallurgy in pre-planarized passivation. That is, as shown in U.S. Pat. No. 4,789,648, issued Dec. 6, 1988 to Chow et al and assigned to the assignee of the present invention (hereinafter the xe2x80x9cChow patentxe2x80x9d), which teaches the method of forming coplanar imbedded lines in insulators where the lines include integral vias to underlying conductive layers. Normally, the horizontal (line) and vertical (via) portions of the metallurgy are formed using two separately formed layers of metal; the Chow patent maximizes conductivity by eliminating the interlayer interface that normally exists between the horizontal and vertical portions of the metallurgy structure.
In the prior art, it is well known to utilize aluminum alloys or tungsten as the metallurgy for integrated circuits. However, the conductivity characteristics of these materials may not be sufficient as the density of semiconductor chips increases below 0.4 microns. These metallurgies are typically deposited on the wafer utilizing chemical vapor deposition, sputtering or other directional deposition techniques. As chip area is reduced the aspect ratio (that is, the ratio of height relative to width) of vias, or openings, formed through passivation increases making it difficult to deposit metal into high aspect ration vias. The result can be the formation of voids in metals deposited resulting in increased resistance or even failure to form useful contacts. In addition, at smaller geometries metal lines become more susceptible to electromigration-induced faults. Thus, the semiconductor industry has recently emphasized the development in the copper metallurgies to replace aluminum-based metallurgy. Although copper has low resistivity and higher electromigration resistance than aluminum, it has no standard deposition technique. No fewer than six different types of depositions methods have been investigated, including chemical vapor deposition, sputtering, evaporation, plasma CVD, electroless and electroplating. Each has its advantages and disadvantages. In addition, several problems are required to be solved before a manufacturable copper technology can be defined.
Copper, which is highly sensitive to corrosion does not form a self-passivating oxide as does aluminum, presents unique challenges, particularly in the area of CMP.
Initial methods of implementing copper in semiconductor devices and planarization by CMP emphasized only the etching and abrasion of copper as evidenced by slurries such as Various slurries for CMP of copper have been proposed in the prior art. These techniques include the following: water, a solid abrasive, an oxidant from one of HNO3, H2SO4, and AgNO3 as taught in U.S. Pat. No. 5,354,490 to, Yu et al.; and water, a solid abrasive, an oxidant: HNO3 or NH4OH and KMnO4 with a H2O2 buffering agent as taught in the article xe2x80x9cInitial study on copper CMP slurry chemistries,xe2x80x9d Ronald Carpio et al., thin solid films, Vol. 266, No. 2, 1 October 1995, pp. 238-244.
Various reagents have been proposed as additives to copper CMP slurries to (1) retard the polishing/etch rate of interlevel dielectrics such as butanol as taught be U.S. Pat. No. 5,614,444 to Farkas et al. or (2) to retard the polish/etch rate of copper such as adding benzotriazole (BTA) as taught in U.S. Pat. No. 5,770,095 to Sasaki et al. or the article xe2x80x9cAlkaline Formulations for Chemical Mechanical Polishing of Copper Utilizing Azole Passivation,xe2x80x9d anonymous, IBM Technical Disclosure Bulletin, Vol. 37, No. 10, October 1994, p. 187.
Because copper has a high diffusion rate in some dielectrics, particularly silicon dioxide, some form of barrier layer between interlevel dielectrics and copper metallurgy is required. Various barrier materials have been proposed including refractory metals such as titanium (Ti), tantalum (Ta), tungsten (W), compounds such as titanium nitride and tantalum nitride, alloys such as TiW, doped metals such as titanium or tantalum doped with nitrogen (Ti(N) or Ta(N)) and bilayers such as Ti/W or Ta/TaN have been proposed by any of several references.
CMP methods proposed to be used to polish or planarize copper metallurgy including under lying barrier materials have in many instances comprised a single slurry and polishing step as taught in U.S. Pat. No. 5,447,887 to Filipiak et al. (single step tantalum, titanium or titanium-tungsten barrier layer, slurry unidentified); U.S. Pat. No. 5,575,885 to Hirabayashi et al. (alkaline slurry with titanium, titanium nitride, niobium, tungsten or a copper-tantalum alloy); U.S. Pat. No. 6,612,254 to Mu et al. (ammonium hydroxide, silica and water with a barrier layer of Titanium nitride) and the article xe2x80x9cCHEMICAL-MECHANICAL POLISHING OF COPPER IN ACIDIC MEDIAxe2x80x9d by Q. Luo et al., 1996 CMP-MIC Conference, Feb. 22-23, 1996, pp. 145-151 (Acidic ferric nitrate,BTA, poly ethylene glycol surfactant, alumina and water with a titanium-tungsten alloy barrier layer).
Recently the evolution of copper CMP has included two-step processes as taught by U.S. Pat. No. 5,676,587 to Landers et al. (copper polish using alumina-based slurry selective to the copper and a silica-based slurry selective to the barrier layer of Ta/TaN) or a three-step process as taught by U.S. Pat. No. 5,516,346 to Cadien et al. (separate slurries for each of copper, tungsten and titanium nitride).
Most recently a barrier layer comprising a first layer of hexagonal phase tantalum nitride and a second layer of alpha-phase tantalum has been proposed in European Patent Application EP 0751566 A2 to Cabral et al. published Jan. 2, 1997.
Finally, co-pending U.S. Provisional application No. 60/105,470 filed Oct. 23, 1998 teaches a slurry for copper comprising water, alumina, an oxidizing agent (ferric nitrate), a copper passivating agent (BTA) and a surfactant (DUPONOL (a Trademark of e.i. du Pont Company SP) which has proved to be highly selective to copper over the liner of Cabral et al. European application EP 0 751 566 A2, as well as other tantalum-based liners.
In general, the prior art set forth above deals with polishing of copper with and without barrier materials in conventional metal line or stud via applications. However, when polishing metal in a dual Damascene environment where both lines and studs may be formed, as shown in the Chow patent, particular challenges are presented that must be addressed in the CMP process. As shown in FIG. 1, oxide 10 has narrow openings 12 that define vias, and wide openings 14 that define the metal lines. Each opening is filled with liner 20 and copper 22. As initially deposited, copper layer 22 extends over portions of barrier layer 20 and is removed by a separate CMP step as described in co-pending Provisional Application Ser. No. 60/105,470 filed Oct. 23, 1998, the teachings of which are incorporated herein by reference. The removal of the overlying copper results in the structure as shown in FIG. 2.
In the invention, the portions of the metal layers 20 and 22 formed above the upper surface of oxide 10 are removed by CMP, utilizing the polishing slurry of the invention. During this operation, two goals are to be achieved. One is to maximize the removal rate of the copper, because the faster the polish process can be achieved the more wafers can be processed per unit time, decreasing the overall cost. Another goal is to remove the copper without appreciably removing the liner, because removal of the liner could lead to partial removal of the underlaying oxide, introducing non-planarity in the final surface and allows the switching to another slurry more selective to the liner. These goals of the copper CMP process (high removal rate of copper, without appreciable removal of the underlaying liner) can often be incompatible; in the prior art, removal rate of the bulk metal is often sacrificed in order to prevent excessive liner removal.
In addition, the copper slurry should minimize dishing and errosion in the polished copper. Ideally, when the CMP process is completed, the upper surface of the copper would be coplanar with the surrounding oxide. This result can be achieved for the copper in the narrow openings 12. However, in the wide openings 14, the pressure of the polish pad on the wafer results in a bowing (or xe2x80x9cdishingxe2x80x9d) profile 22A, in which the thickness of the copper at the center of the wide opening is less than the thickness at either end. In general, this structure is to be avoided, because it reintroduces non-planarity in the final BEOL structure and reduces the thickness of lateral interconnects such as line structures 14. Errosion is the removal of the non-copper regions between narrow lines in high density wiring areas. That is, it is undesirable for the planarization slurry to be yoo aggressive in removing the interlevel dielectric (ILD) between lines once the ILD has been exposed.
Therefore, another object of the present invention is to provide a CMP process that minimizes dishing and errosion. The specific goal is to prevent the difference between the thin and thick regions of the copper within opening 14 from being greater than the thickness of the liner 14 disposed on the upper surface of the oxide 10.
In the invention, a liner or barrier layer for copper metallurgy comprising a refractory and/or its alloys and compounds is removed by CMP in an acidic slurry of an oxidizer such as hydrogen peroxide, deionized water, a corrosion inhibitor such as benzotriazole, and a surfactant such as DUPONOL SP, resulting in a high removal rate of the liner including any remaining copper without appreciable removal of the underlying insulator layer.